1. Field of the Invention
The present invention relates to a semiconductor device and testing method thereof, and more particularly relates to a semiconductor device constituted by a plurality of core chips and an interface chip that controls the core chips, and a testing method thereof.
2. Description of the Related Art
Memory capacities required for semiconductor memory devices such as a DRAM (Dynamic Random Access Memory) are increasing year by year. To satisfy this requirement, a memory device called “multi chip package” having a plurality of memory chips stacked has been proposed in recent years. In the multi chip package, however, ordinary memory chips that can operate independently by themselves are used. The ordinary memory chip includes a so-called front end unit that establishes interface to outside (a memory controller, for example). Accordingly, a chip area that a memory core can be formed in each memory chip is limited by existence of the front end unit. It is therefore difficult to greatly increase a memory capacity of one memory chip.
Additionally, although the front end unit is a logic circuit, transistors including the front end unit are fabricated at the same time as transistors including a back end unit constituting a memory core. Therefore, it is difficult to speed-up the transistors of the front end unit.
To solve these problems, a method that enables to constitute one semiconductor memory device by integrating a front end unit and a back end unit on separate chips, respectively, and stacking these chips has been proposed. According to this method, the chip areas that the memory core can be formed become larger in the plural core chips, and therefore the memory capacity of one core chip can be increased. On the other hand, an interface chip that has the front end unit can be fabricated by a process different from the memory core, which allows the logic circuits to be formed by a high-speed transistor. Furthermore, because the plural core chips can be allocated to one interface chip, a semiconductor memory device with a quite large capacity and a high speed operation can be provided.
In a semiconductor device using an interface chip, adjacent chips are electrically connected to each other by a large number of through silicon vias penetrating through silicon substrates of core chips. Most of the through silicon vias are short-circuited to through silicon vias in other chips provided at same positions as seen in a planar view from a stacking direction. A current path or a current path line for connecting the interface chip to each core chip is formed by a plurality of through silicon vias electrically short-circuited one another.
Japanese Patent Application Laid-Open No. 2000-221226 discloses a technique of detecting short-circuit defects or the like of a plurality of bus lines that connect a measuring IC and a measurement target IC. With this technique, the measuring IC transmits data representing a predetermined logical value (“0” or “1”) to the bus lines. The measurement target IC receives this data via the bus lines, inverts the logical value of the data, and returns data representing an inverted logical value. The measuring IC compares the logical value of the transmitted data with the logical value of the returned data, and determines that the data is normal when the logical values do not match and that the data is abnormal when the logical values match each other.
Meanwhile, in a semiconductor device using an interface chip, a short-circuit defect sometimes occurs between adjacent current paths or between a current path and a power supply wiring or ground wiring. The current path having short-circuit defects is detected in a testing process, and replaced by another normal current path in a relieving process.
The testing process, as in the technique of Japanese Patent Application Laid-Open No. 2000-221226 for example, could be configured that the measuring IC transmits data representing a predetermined logical value to one end of a current path, and the measurement target IC returns data representing an inverted logical value to the measuring IC from the other end of the current path, and thus the measuring IC detects a short-circuit defect that has occurred to the current path. Since it is preferable that short-circuit defects are detected in the interface chip, in the above case, a testing circuit is preferably constituted so that the interface chip serves as the measuring IC.
However, the above conventional technique has the following problems. That is, if the testing circuit is constituted as described above, it is necessary to provide circuits that perform a process of inverting the logical value in each core chip, which is the measurement target IC. This unfavorably leads to a reduction in a storage capacity per core chip. Therefore, there has been a demand for a detecting technique that does not require any provision of circuits that perform a process of inverting the logic value in each core chip.